feature: rename MinerModels to MinerModel, and add device info in as properties of MinerData.
This commit is contained in:
@@ -75,6 +75,9 @@ class MinerData:
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# about
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device_info: DeviceInfo = None
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make: str = field(init=False)
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model: str = field(init=False)
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firmware: str = field(init=False)
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mac: str = None
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api_ver: str = None
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fw_ver: str = None
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@@ -332,6 +335,33 @@ class MinerData:
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def timestamp(self, val):
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pass
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@property
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def make(self): # noqa - Skip PyCharm inspection
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if self.device_info.make is not None:
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return str(self.device_info.make)
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@make.setter
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def make(self, val):
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pass
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@property
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def model(self): # noqa - Skip PyCharm inspection
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if self.device_info.model is not None:
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return str(self.device_info.model)
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@model.setter
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def model(self, val):
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pass
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@property
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def firmware(self): # noqa - Skip PyCharm inspection
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if self.device_info.firmware is not None:
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return str(self.device_info.firmware)
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@firmware.setter
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def firmware(self, val):
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pass
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def asdict(self) -> dict:
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return asdict(self, dict_factory=self.dict_factory)
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@@ -2,10 +2,11 @@ from dataclasses import dataclass
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from pyasic.device.firmware import MinerFirmware
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from pyasic.device.makes import MinerMake
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from pyasic.device.models import MinerModel
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@dataclass
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class DeviceInfo:
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make: MinerMake = None
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model: str = None
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model: MinerModel = None
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firmware: MinerFirmware = None
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@@ -0,0 +1,3 @@
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from .firmware import MinerFirmware
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from .makes import MinerMake
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from .models import MinerModel
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@@ -308,7 +308,7 @@ class AuradineModels(StrEnum):
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AD3500 = "AD3500"
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class MinerModels:
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class MinerModel:
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ANTMINER = AntminerModels
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WHATSMINER = WhatsminerModels
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AVALONMINER = AvalonminerModels
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class Z15(AntMinerMake):
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raw_model = MinerModels.ANTMINER.Z15
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raw_model = MinerModel.ANTMINER.Z15
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expected_chips = 3
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@@ -13,33 +13,33 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class S17(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S17
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raw_model = MinerModel.ANTMINER.S17
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expected_chips = 48
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expected_fans = 4
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class S17Plus(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S17Plus
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raw_model = MinerModel.ANTMINER.S17Plus
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expected_chips = 65
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expected_fans = 4
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class S17Pro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S17Pro
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raw_model = MinerModel.ANTMINER.S17Pro
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expected_chips = 48
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expected_fans = 4
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class S17e(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S17e
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raw_model = MinerModel.ANTMINER.S17e
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expected_chips = 135
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expected_fans = 4
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@@ -13,26 +13,26 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class T17(AntMinerMake):
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raw_model = MinerModels.ANTMINER.T17
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raw_model = MinerModel.ANTMINER.T17
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expected_chips = 30
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expected_fans = 4
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class T17Plus(AntMinerMake):
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raw_model = MinerModels.ANTMINER.T17Plus
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raw_model = MinerModel.ANTMINER.T17Plus
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expected_chips = 44
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expected_fans = 4
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class T17e(AntMinerMake):
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raw_model = MinerModels.ANTMINER.T17e
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raw_model = MinerModel.ANTMINER.T17e
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expected_chips = 78
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expected_fans = 4
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@@ -13,138 +13,138 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class S19(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19
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raw_model = MinerModel.ANTMINER.S19
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expected_chips = 76
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expected_fans = 4
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class S19NoPIC(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19NoPIC
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raw_model = MinerModel.ANTMINER.S19NoPIC
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expected_chips = 88
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expected_fans = 4
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class S19Pro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19Pro
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raw_model = MinerModel.ANTMINER.S19Pro
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expected_chips = 114
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expected_fans = 4
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class S19i(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19i
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raw_model = MinerModel.ANTMINER.S19i
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expected_chips = 80
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expected_fans = 4
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class S19Plus(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19Plus
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raw_model = MinerModel.ANTMINER.S19Plus
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expected_chips = 80
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expected_fans = 4
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class S19ProPlus(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19ProPlus
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raw_model = MinerModel.ANTMINER.S19ProPlus
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expected_chips = 120
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expected_fans = 4
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class S19XP(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19XP
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raw_model = MinerModel.ANTMINER.S19XP
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expected_chips = 110
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expected_fans = 4
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class S19a(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19a
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raw_model = MinerModel.ANTMINER.S19a
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expected_chips = 72
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expected_fans = 4
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class S19aPro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19aPro
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raw_model = MinerModel.ANTMINER.S19aPro
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expected_chips = 100
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expected_fans = 4
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class S19j(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19j
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raw_model = MinerModel.ANTMINER.S19j
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expected_chips = 114
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expected_fans = 4
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class S19jNoPIC(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19jNoPIC
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raw_model = MinerModel.ANTMINER.S19jNoPIC
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expected_chips = 88
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expected_fans = 4
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class S19jPro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19jPro
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raw_model = MinerModel.ANTMINER.S19jPro
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expected_chips = 126
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expected_fans = 4
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class S19jProNoPIC(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19jProNoPIC
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raw_model = MinerModel.ANTMINER.S19jProNoPIC
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expected_chips = 126
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expected_fans = 4
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class S19jProPlus(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19jProPlus
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raw_model = MinerModel.ANTMINER.S19jProPlus
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expected_chips = 120
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expected_fans = 4
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class S19jProPlusNoPIC(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19jProPlusNoPIC
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raw_model = MinerModel.ANTMINER.S19jProPlusNoPIC
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expected_chips = 120
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expected_fans = 4
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class S19kPro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19kPro
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raw_model = MinerModel.ANTMINER.S19kPro
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expected_chips = 77
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expected_fans = 4
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class S19kProNoPIC(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19kProNoPIC
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raw_model = MinerModel.ANTMINER.S19kProNoPIC
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expected_chips = 77
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expected_fans = 4
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class S19L(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19L
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raw_model = MinerModel.ANTMINER.S19L
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expected_chips = 76
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expected_fans = 4
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class S19Hydro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19Hydro
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raw_model = MinerModel.ANTMINER.S19Hydro
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expected_chips = 104
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expected_hashboards = 4
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@@ -152,7 +152,7 @@ class S19Hydro(AntMinerMake):
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class S19ProHydro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19ProHydro
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raw_model = MinerModel.ANTMINER.S19ProHydro
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expected_chips = 180
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expected_hashboards = 4
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@@ -160,7 +160,7 @@ class S19ProHydro(AntMinerMake):
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class S19ProPlusHydro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19ProPlusHydro
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raw_model = MinerModel.ANTMINER.S19ProPlusHydro
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expected_chips = 180
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expected_hashboards = 4
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@@ -168,7 +168,7 @@ class S19ProPlusHydro(AntMinerMake):
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class S19KPro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S19KPro
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raw_model = MinerModel.ANTMINER.S19KPro
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expected_chips = 77
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expected_fans = 4
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@@ -13,12 +13,12 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class T19(AntMinerMake):
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raw_model = MinerModels.ANTMINER.T19
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raw_model = MinerModel.ANTMINER.T19
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expected_chips = 76
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expected_fans = 4
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@@ -13,12 +13,12 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class S21(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S21
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raw_model = MinerModel.ANTMINER.S21
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expected_chips = 108
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expected_fans = 4
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@@ -13,12 +13,12 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class T21(AntMinerMake):
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raw_model = MinerModels.ANTMINER.T21
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raw_model = MinerModel.ANTMINER.T21
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expected_chips = 108
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expected_fans = 4
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class D3(AntMinerMake):
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raw_model = MinerModels.ANTMINER.D3
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raw_model = MinerModel.ANTMINER.D3
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expected_chips = 60
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class HS3(AntMinerMake):
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raw_model = MinerModels.ANTMINER.HS3
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raw_model = MinerModel.ANTMINER.HS3
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expected_chips = 92
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class L3Plus(AntMinerMake):
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raw_model = MinerModels.ANTMINER
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raw_model = MinerModel.ANTMINER
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expected_chips = 72
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class DR5(AntMinerMake):
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raw_model = MinerModels.ANTMINER.DR5
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raw_model = MinerModel.ANTMINER.DR5
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expected_chips = 72
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@@ -13,12 +13,12 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class L7(AntMinerMake):
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raw_model = MinerModels.ANTMINER.L7
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raw_model = MinerModel.ANTMINER.L7
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expected_chips = 120
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expected_fans = 4
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@@ -13,12 +13,12 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class E9Pro(AntMinerMake):
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raw_model = MinerModels.ANTMINER.E9Pro
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raw_model = MinerModel.ANTMINER.E9Pro
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expected_chips = 8
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expected_hashboards = 2
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@@ -13,23 +13,23 @@
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# See the License for the specific language governing permissions and -
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# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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class S9(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S9
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raw_model = MinerModel.ANTMINER.S9
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expected_chips = 63
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class S9i(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S9i
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raw_model = MinerModel.ANTMINER.S9i
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expected_chips = 63
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class S9j(AntMinerMake):
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raw_model = MinerModels.ANTMINER.S9j
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raw_model = MinerModel.ANTMINER.S9j
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expected_chips = 63
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@@ -13,11 +13,11 @@
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# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
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# ------------------------------------------------------------------------------
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from pyasic.device.models import MinerModels
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from pyasic.device.models import MinerModel
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from pyasic.miners.device.makes import AntMinerMake
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|
||||
|
||||
class T9(AntMinerMake):
|
||||
raw_model = MinerModels.ANTMINER.T9
|
||||
raw_model = MinerModel.ANTMINER.T9
|
||||
|
||||
expected_chips = 54
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAD2500(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AD2500
|
||||
raw_model = MinerModel.AURADINE.AD2500
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAD3500(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AD3500
|
||||
raw_model = MinerModel.AURADINE.AD3500
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAI2500(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AI2500
|
||||
raw_model = MinerModel.AURADINE.AI2500
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAI3680(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AI3680
|
||||
raw_model = MinerModel.AURADINE.AI3680
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAT1500(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AT1500
|
||||
raw_model = MinerModel.AURADINE.AT1500
|
||||
|
||||
expected_chips = 132
|
||||
expected_fans = 4
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AuradineMake
|
||||
|
||||
|
||||
class AuradineAT2860(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AT2860
|
||||
raw_model = MinerModel.AURADINE.AT2860
|
||||
|
||||
expected_fans = 4
|
||||
|
||||
|
||||
class AuradineAT2880(AuradineMake):
|
||||
raw_model = MinerModels.AURADINE.AT2880
|
||||
raw_model = MinerModel.AURADINE.AT2880
|
||||
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon1026(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon1026
|
||||
raw_model = MinerModel.AVALONMINER.Avalon1026
|
||||
|
||||
expected_chips = 80
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon1047(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon1047
|
||||
raw_model = MinerModel.AVALONMINER.Avalon1047
|
||||
|
||||
expected_chips = 80
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon1066(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon1066
|
||||
raw_model = MinerModel.AVALONMINER.Avalon1066
|
||||
expected_chips = 114
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon1166Pro(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon1166Pro
|
||||
raw_model = MinerModel.AVALONMINER.Avalon1166Pro
|
||||
|
||||
expected_chips = 120
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon1246(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon1246
|
||||
raw_model = MinerModel.AVALONMINER.Avalon1246
|
||||
|
||||
expected_chips = 120
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon721(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon721
|
||||
raw_model = MinerModel.AVALONMINER.Avalon721
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 18
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon741(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon741
|
||||
raw_model = MinerModel.AVALONMINER.Avalon741
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 22
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon761(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon761
|
||||
raw_model = MinerModel.AVALONMINER.Avalon761
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 18
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon821(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon821
|
||||
raw_model = MinerModel.AVALONMINER.Avalon821
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 26
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon841(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon841
|
||||
raw_model = MinerModel.AVALONMINER.Avalon841
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 26
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon851(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon851
|
||||
raw_model = MinerModel.AVALONMINER.Avalon851
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 26
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import AvalonMinerMake
|
||||
|
||||
|
||||
class Avalon921(AvalonMinerMake):
|
||||
raw_model = MinerModels.AVALONMINER.Avalon921
|
||||
raw_model = MinerModel.AVALONMINER.Avalon921
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 26
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import ePICMake
|
||||
|
||||
|
||||
class BlockMiner520i(ePICMake):
|
||||
raw_model = MinerModels.EPIC.BM520i
|
||||
raw_model = MinerModel.EPIC.BM520i
|
||||
|
||||
expected_chips = 124
|
||||
expected_fans = 4
|
||||
|
||||
|
||||
class BlockMiner720i(ePICMake):
|
||||
raw_model = MinerModels.EPIC.BM720i
|
||||
raw_model = MinerModel.EPIC.BM720i
|
||||
|
||||
expected_chips = 180
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import GoldshellMake
|
||||
|
||||
|
||||
class CK5(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.CK5
|
||||
raw_model = MinerModel.GOLDSHELL.CK5
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 46
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import GoldshellMake
|
||||
|
||||
|
||||
class HS5(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.HS5
|
||||
raw_model = MinerModel.GOLDSHELL.HS5
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 46
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import GoldshellMake
|
||||
|
||||
|
||||
class KD5(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.KD5
|
||||
raw_model = MinerModel.GOLDSHELL.KD5
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 46
|
||||
|
||||
@@ -13,19 +13,19 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import GoldshellMake
|
||||
|
||||
|
||||
class KDBoxII(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.KDBoxII
|
||||
raw_model = MinerModel.GOLDSHELL.KDBoxII
|
||||
|
||||
expected_chips = 36
|
||||
expected_hashboards = 1
|
||||
|
||||
|
||||
class KDBoxPro(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.KDBoxPro
|
||||
raw_model = MinerModel.GOLDSHELL.KDBoxPro
|
||||
|
||||
expected_chips = 16
|
||||
expected_hashboards = 1
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import GoldshellMake
|
||||
|
||||
|
||||
class KDMax(GoldshellMake):
|
||||
raw_model = MinerModels.GOLDSHELL.KDMax
|
||||
raw_model = MinerModel.GOLDSHELL.KDMax
|
||||
|
||||
expected_chips = 84
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,9 +13,9 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import InnosiliconMake
|
||||
|
||||
|
||||
class A10X(InnosiliconMake):
|
||||
raw_model = MinerModels.INNOSILICON.A10X
|
||||
raw_model = MinerModel.INNOSILICON.A10X
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import InnosiliconMake
|
||||
|
||||
|
||||
class T3HPlus(InnosiliconMake):
|
||||
raw_model = MinerModels.INNOSILICON.T3HPlus
|
||||
raw_model = MinerModel.INNOSILICON.T3HPlus
|
||||
|
||||
expected_chips = 114
|
||||
expected_fans = 4
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M20V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20V10
|
||||
raw_model = MinerModel.WHATSMINER.M20V10
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M20PV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20PV10
|
||||
raw_model = MinerModel.WHATSMINER.M20PV10
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M20PV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20PV30
|
||||
raw_model = MinerModel.WHATSMINER.M20PV30
|
||||
|
||||
expected_chips = 148
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M20SV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20SV10
|
||||
raw_model = MinerModel.WHATSMINER.M20SV10
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M20SV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20SV20
|
||||
raw_model = MinerModel.WHATSMINER.M20SV20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M20SV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20SV30
|
||||
raw_model = MinerModel.WHATSMINER.M20SV30
|
||||
|
||||
expected_chips = 140
|
||||
|
||||
@@ -13,9 +13,9 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M20SPlusV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M20SPlusV30
|
||||
raw_model = MinerModel.WHATSMINER.M20SPlusV30
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M21V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M21V10
|
||||
raw_model = MinerModel.WHATSMINER.M21V10
|
||||
|
||||
expected_chips = 33
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M21SV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M21SV20
|
||||
raw_model = MinerModel.WHATSMINER.M21SV20
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M21SV60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M21SV60
|
||||
raw_model = MinerModel.WHATSMINER.M21SV60
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M21SV70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M21SV70
|
||||
raw_model = MinerModel.WHATSMINER.M21SV70
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
@@ -13,9 +13,9 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M21SPlusV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M21SPlusV20
|
||||
raw_model = MinerModel.WHATSMINER.M21SPlusV20
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M29V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M29V10
|
||||
raw_model = MinerModel.WHATSMINER.M29V10
|
||||
|
||||
expected_chips = 50
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30V10
|
||||
raw_model = MinerModel.WHATSMINER.M30V10
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M30V20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30V20
|
||||
raw_model = MinerModel.WHATSMINER.M30V20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30KV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30KV10
|
||||
raw_model = MinerModel.WHATSMINER.M30KV10
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 240
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30LV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30LV10
|
||||
raw_model = MinerModel.WHATSMINER.M30LV10
|
||||
|
||||
board_num = 4
|
||||
expected_chips = 144
|
||||
|
||||
@@ -13,169 +13,169 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30SV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV10
|
||||
raw_model = MinerModel.WHATSMINER.M30SV10
|
||||
|
||||
expected_chips = 148
|
||||
|
||||
|
||||
class M30SV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV20
|
||||
raw_model = MinerModel.WHATSMINER.M30SV20
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M30SV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV30
|
||||
raw_model = MinerModel.WHATSMINER.M30SV30
|
||||
|
||||
expected_chips = 164
|
||||
|
||||
|
||||
class M30SV40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV40
|
||||
raw_model = MinerModel.WHATSMINER.M30SV40
|
||||
|
||||
expected_chips = 172
|
||||
|
||||
|
||||
class M30SV50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV50
|
||||
raw_model = MinerModel.WHATSMINER.M30SV50
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M30SV60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV60
|
||||
raw_model = MinerModel.WHATSMINER.M30SV60
|
||||
|
||||
expected_chips = 164
|
||||
|
||||
|
||||
class M30SV70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV70
|
||||
raw_model = MinerModel.WHATSMINER.M30SV70
|
||||
|
||||
|
||||
class M30SV80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SV80
|
||||
raw_model = MinerModel.WHATSMINER.M30SV80
|
||||
|
||||
expected_chips = 129
|
||||
|
||||
|
||||
class M30SVE10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE10
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE10
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M30SVE20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE20
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M30SVE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE30
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE30
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M30SVE40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE40
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE40
|
||||
|
||||
expected_chips = 123
|
||||
|
||||
|
||||
class M30SVE50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE50
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE50
|
||||
|
||||
expected_chips = 129
|
||||
|
||||
|
||||
class M30SVE60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE60
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE60
|
||||
|
||||
|
||||
class M30SVE70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVE70
|
||||
raw_model = MinerModel.WHATSMINER.M30SVE70
|
||||
|
||||
|
||||
class M30SVF10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVF10
|
||||
raw_model = MinerModel.WHATSMINER.M30SVF10
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M30SVF20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVF20
|
||||
raw_model = MinerModel.WHATSMINER.M30SVF20
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M30SVF30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVF30
|
||||
raw_model = MinerModel.WHATSMINER.M30SVF30
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M30SVG10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVG10
|
||||
raw_model = MinerModel.WHATSMINER.M30SVG10
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M30SVG20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVG20
|
||||
raw_model = MinerModel.WHATSMINER.M30SVG20
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M30SVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVG30
|
||||
raw_model = MinerModel.WHATSMINER.M30SVG30
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M30SVG40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVG40
|
||||
raw_model = MinerModel.WHATSMINER.M30SVG40
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M30SVH10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH10
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH10
|
||||
|
||||
expected_chips = 64
|
||||
|
||||
|
||||
class M30SVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH20
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH20
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M30SVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH30
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH30
|
||||
|
||||
|
||||
class M30SVH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH40
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH40
|
||||
|
||||
expected_chips = 64
|
||||
|
||||
|
||||
class M30SVH50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH50
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH50
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M30SVH60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVH60
|
||||
raw_model = MinerModel.WHATSMINER.M30SVH60
|
||||
|
||||
|
||||
class M30SVI20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SVI20
|
||||
raw_model = MinerModel.WHATSMINER.M30SVI20
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
@@ -13,181 +13,181 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30SPlusV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV10
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV10
|
||||
|
||||
expected_chips = 215
|
||||
|
||||
|
||||
class M30SPlusV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV20
|
||||
|
||||
expected_chips = 255
|
||||
|
||||
|
||||
class M30SPlusV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV30
|
||||
|
||||
|
||||
class M30SPlusV40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV40
|
||||
|
||||
expected_chips = 235
|
||||
|
||||
|
||||
class M30SPlusV50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV50
|
||||
|
||||
expected_chips = 225
|
||||
|
||||
|
||||
class M30SPlusV60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV60
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV60
|
||||
|
||||
expected_chips = 245
|
||||
|
||||
|
||||
class M30SPlusV70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV70
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV70
|
||||
|
||||
expected_chips = 235
|
||||
|
||||
|
||||
class M30SPlusV80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV80
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV80
|
||||
|
||||
expected_chips = 245
|
||||
|
||||
|
||||
class M30SPlusV90(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV90
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV90
|
||||
|
||||
expected_chips = 225
|
||||
|
||||
|
||||
class M30SPlusV100(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusV100
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusV100
|
||||
|
||||
expected_chips = 215
|
||||
|
||||
|
||||
class M30SPlusVE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE30
|
||||
|
||||
expected_chips = 148
|
||||
|
||||
|
||||
class M30SPlusVE40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE40
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M30SPlusVE50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE50
|
||||
|
||||
expected_chips = 164
|
||||
|
||||
|
||||
class M30SPlusVE60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE60
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE60
|
||||
|
||||
expected_chips = 172
|
||||
|
||||
|
||||
class M30SPlusVE70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE70
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE70
|
||||
|
||||
|
||||
class M30SPlusVE80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE80
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE80
|
||||
|
||||
|
||||
class M30SPlusVE90(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE90
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE90
|
||||
|
||||
|
||||
class M30SPlusVE100(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVE100
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVE100
|
||||
|
||||
|
||||
class M30SPlusVF20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVF20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVF20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M30SPlusVF30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVF30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVF30
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M30SPlusVG20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVG20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVG20
|
||||
|
||||
expected_chips = 82
|
||||
|
||||
|
||||
class M30SPlusVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVG30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVG30
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M30SPlusVG40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVG40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVG40
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M30SPlusVG50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVG50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVG50
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M30SPlusVG60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVG60
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVG60
|
||||
|
||||
expected_chips = 86
|
||||
|
||||
|
||||
class M30SPlusVH10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH10
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH10
|
||||
|
||||
expected_chips = 64
|
||||
|
||||
|
||||
class M30SPlusVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH20
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M30SPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH30
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M30SPlusVH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH40
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M30SPlusVH50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH50
|
||||
|
||||
expected_chips = 64
|
||||
|
||||
|
||||
class M30SPlusVH60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusVH60
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusVH60
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
@@ -13,109 +13,109 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M30SPlusPlusV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusV10
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusV10
|
||||
expected_hashboards = 4
|
||||
expected_chips = 255
|
||||
|
||||
|
||||
class M30SPlusPlusV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusV20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusV20
|
||||
expected_hashboards = 4
|
||||
expected_chips = 255
|
||||
|
||||
|
||||
class M30SPlusPlusVE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVE30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVE30
|
||||
expected_chips = 215
|
||||
|
||||
|
||||
class M30SPlusPlusVE40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVE40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVE40
|
||||
expected_chips = 225
|
||||
|
||||
|
||||
class M30SPlusPlusVE50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVE50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVE50
|
||||
expected_chips = 235
|
||||
|
||||
|
||||
class M30SPlusPlusVF40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVF40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVF40
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M30SPlusPlusVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVG30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVG30
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M30SPlusPlusVG40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVG40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVG40
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M30SPlusPlusVG50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVG50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVG50
|
||||
|
||||
|
||||
class M30SPlusPlusVH10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH10
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH10
|
||||
expected_chips = 82
|
||||
|
||||
|
||||
class M30SPlusPlusVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH20
|
||||
expected_chips = 86
|
||||
|
||||
|
||||
class M30SPlusPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH30
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M30SPlusPlusVH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH40
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH40
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M30SPlusPlusVH50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH50
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH50
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M30SPlusPlusVH60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH60
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH60
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M30SPlusPlusVH70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH70
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH70
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M30SPlusPlusVH80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH80
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH80
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M30SPlusPlusVH90(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH90
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH90
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M30SPlusPlusVH100(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVH100
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVH100
|
||||
expected_chips = 82
|
||||
|
||||
|
||||
class M30SPlusPlusVJ20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVJ20
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVJ20
|
||||
|
||||
|
||||
class M30SPlusPlusVJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M30SPlusPlusVJ30
|
||||
raw_model = MinerModel.WHATSMINER.M30SPlusPlusVJ30
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31V10
|
||||
raw_model = MinerModel.WHATSMINER.M31V10
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M31V20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31V20
|
||||
raw_model = MinerModel.WHATSMINER.M31V20
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
@@ -13,19 +13,19 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31HV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31HV10
|
||||
raw_model = MinerModel.WHATSMINER.M31HV10
|
||||
|
||||
expected_chips = 114
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M31HV40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31HV40
|
||||
raw_model = MinerModel.WHATSMINER.M31HV40
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 136
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31LV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31LV10
|
||||
raw_model = MinerModel.WHATSMINER.M31LV10
|
||||
|
||||
expected_chips = 114
|
||||
|
||||
@@ -13,73 +13,73 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31SV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV10
|
||||
raw_model = MinerModel.WHATSMINER.M31SV10
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M31SV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV20
|
||||
raw_model = MinerModel.WHATSMINER.M31SV20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M31SV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV30
|
||||
raw_model = MinerModel.WHATSMINER.M31SV30
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M31SV40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV40
|
||||
raw_model = MinerModel.WHATSMINER.M31SV40
|
||||
|
||||
expected_chips = 123
|
||||
|
||||
|
||||
class M31SV50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV50
|
||||
raw_model = MinerModel.WHATSMINER.M31SV50
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M31SV60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV60
|
||||
raw_model = MinerModel.WHATSMINER.M31SV60
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M31SV70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV70
|
||||
raw_model = MinerModel.WHATSMINER.M31SV70
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M31SV80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV80
|
||||
raw_model = MinerModel.WHATSMINER.M31SV80
|
||||
|
||||
|
||||
class M31SV90(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SV90
|
||||
raw_model = MinerModel.WHATSMINER.M31SV90
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M31SVE10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SVE10
|
||||
raw_model = MinerModel.WHATSMINER.M31SVE10
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
|
||||
class M31SVE20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SVE20
|
||||
raw_model = MinerModel.WHATSMINER.M31SVE20
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
|
||||
class M31SVE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SVE30
|
||||
raw_model = MinerModel.WHATSMINER.M31SVE30
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31SEV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SEV10
|
||||
raw_model = MinerModel.WHATSMINER.M31SEV10
|
||||
|
||||
expected_chips = 82
|
||||
|
||||
|
||||
class M31SEV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SEV20
|
||||
raw_model = MinerModel.WHATSMINER.M31SEV20
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M31SEV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SEV30
|
||||
raw_model = MinerModel.WHATSMINER.M31SEV30
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
@@ -13,119 +13,119 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M31SPlusV10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV10
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV10
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M31SPlusV20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV20
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M31SPlusV30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV30
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV30
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M31SPlusV40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV40
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV40
|
||||
|
||||
expected_chips = 123
|
||||
|
||||
|
||||
class M31SPlusV50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV50
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV50
|
||||
|
||||
expected_chips = 148
|
||||
|
||||
|
||||
class M31SPlusV60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV60
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV60
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M31SPlusV80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV80
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV80
|
||||
|
||||
expected_chips = 129
|
||||
|
||||
|
||||
class M31SPlusV90(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV90
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV90
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M31SPlusV100(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusV100
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusV100
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M31SPlusVE10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE10
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE10
|
||||
|
||||
expected_chips = 82
|
||||
|
||||
|
||||
class M31SPlusVE20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE20
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE20
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M31SPlusVE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE30
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE30
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M31SPlusVE40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE40
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE40
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M31SPlusVE50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE50
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE50
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M31SPlusVE60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE60
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE60
|
||||
|
||||
|
||||
class M31SPlusVE80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVE80
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVE80
|
||||
|
||||
|
||||
class M31SPlusVF20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVF20
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVF20
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M31SPlusVF30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVF30
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVF30
|
||||
|
||||
|
||||
class M31SPlusVG20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVG20
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVG20
|
||||
|
||||
expected_chips = 66
|
||||
|
||||
|
||||
class M31SPlusVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M31SPlusVG30
|
||||
raw_model = MinerModel.WHATSMINER.M31SPlusVG30
|
||||
|
||||
expected_chips = 70
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M32V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M32V10
|
||||
raw_model = MinerModel.WHATSMINER.M32V10
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M32V20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M32V20
|
||||
raw_model = MinerModel.WHATSMINER.M32V20
|
||||
|
||||
expected_chips = 74
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M32S(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M32S
|
||||
raw_model = MinerModel.WHATSMINER.M32S
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
@@ -13,26 +13,26 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M33V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33V10
|
||||
raw_model = MinerModel.WHATSMINER.M33V10
|
||||
|
||||
expected_chips = 33
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M33V20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33V20
|
||||
raw_model = MinerModel.WHATSMINER.M33V20
|
||||
|
||||
expected_chips = 62
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M33V30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33V30
|
||||
raw_model = MinerModel.WHATSMINER.M33V30
|
||||
|
||||
expected_chips = 66
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M33SVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SVG30
|
||||
raw_model = MinerModel.WHATSMINER.M33SVG30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 116
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M33SPlusVG20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusVG20
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusVG20
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 112
|
||||
@@ -26,7 +26,7 @@ class M33SPlusVG20(WhatsMinerMake):
|
||||
|
||||
|
||||
class M33SPlusVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusVH20
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusVH20
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 100
|
||||
@@ -34,7 +34,7 @@ class M33SPlusVH20(WhatsMinerMake):
|
||||
|
||||
|
||||
class M33SPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusVH30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M33SPlusPlusVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusPlusVH20
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusPlusVH20
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 112
|
||||
@@ -26,14 +26,14 @@ class M33SPlusPlusVH20(WhatsMinerMake):
|
||||
|
||||
|
||||
class M33SPlusPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusPlusVH30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M33SPlusPlusVG40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M33SPlusPlusVG40
|
||||
raw_model = MinerModel.WHATSMINER.M33SPlusPlusVG40
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 174
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M34SPlusVE10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M34SPlusVE10
|
||||
raw_model = MinerModel.WHATSMINER.M34SPlusVE10
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 116
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M36SVE10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M36SVE10
|
||||
raw_model = MinerModel.WHATSMINER.M36SVE10
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 114
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M36SPlusVG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M36SPlusVG30
|
||||
raw_model = MinerModel.WHATSMINER.M36SPlusVG30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 108
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M36SPlusPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M36SPlusPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M36SPlusPlusVH30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 80
|
||||
|
||||
@@ -13,26 +13,26 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M39V10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M39V10
|
||||
raw_model = MinerModel.WHATSMINER.M39V10
|
||||
|
||||
expected_chips = 50
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M39V20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M39V20
|
||||
raw_model = MinerModel.WHATSMINER.M39V20
|
||||
|
||||
expected_chips = 54
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M39V30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M39V30
|
||||
raw_model = MinerModel.WHATSMINER.M39V30
|
||||
|
||||
expected_chips = 68
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,76 +13,76 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M50VE30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VE30
|
||||
raw_model = MinerModel.WHATSMINER.M50VE30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 255
|
||||
|
||||
|
||||
class M50VG30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VG30
|
||||
raw_model = MinerModel.WHATSMINER.M50VG30
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M50VH10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH10
|
||||
raw_model = MinerModel.WHATSMINER.M50VH10
|
||||
|
||||
expected_chips = 86
|
||||
|
||||
|
||||
class M50VH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH20
|
||||
raw_model = MinerModel.WHATSMINER.M50VH20
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M50VH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH30
|
||||
raw_model = MinerModel.WHATSMINER.M50VH30
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M50VH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH40
|
||||
raw_model = MinerModel.WHATSMINER.M50VH40
|
||||
|
||||
expected_chips = 84
|
||||
|
||||
|
||||
class M50VH50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH50
|
||||
raw_model = MinerModel.WHATSMINER.M50VH50
|
||||
|
||||
expected_chips = 105
|
||||
|
||||
|
||||
class M50VH60(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH60
|
||||
raw_model = MinerModel.WHATSMINER.M50VH60
|
||||
|
||||
expected_chips = 84
|
||||
|
||||
|
||||
class M50VH70(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH70
|
||||
raw_model = MinerModel.WHATSMINER.M50VH70
|
||||
|
||||
|
||||
class M50VH80(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VH80
|
||||
raw_model = MinerModel.WHATSMINER.M50VH80
|
||||
|
||||
expected_chips = 111
|
||||
|
||||
|
||||
class M50VJ10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VJ10
|
||||
raw_model = MinerModel.WHATSMINER.M50VJ10
|
||||
|
||||
|
||||
class M50VJ20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VJ20
|
||||
raw_model = MinerModel.WHATSMINER.M50VJ20
|
||||
|
||||
|
||||
class M50VJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50VJ30
|
||||
raw_model = MinerModel.WHATSMINER.M50VJ30
|
||||
|
||||
@@ -13,41 +13,41 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M50SVJ10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVJ10
|
||||
raw_model = MinerModel.WHATSMINER.M50SVJ10
|
||||
|
||||
|
||||
class M50SVJ20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVJ20
|
||||
raw_model = MinerModel.WHATSMINER.M50SVJ20
|
||||
|
||||
|
||||
class M50SVJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVJ30
|
||||
raw_model = MinerModel.WHATSMINER.M50SVJ30
|
||||
|
||||
|
||||
class M50SVH10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVH10
|
||||
raw_model = MinerModel.WHATSMINER.M50SVH10
|
||||
|
||||
|
||||
class M50SVH20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVH20
|
||||
raw_model = MinerModel.WHATSMINER.M50SVH20
|
||||
|
||||
expected_chips = 135
|
||||
|
||||
|
||||
class M50SVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVH30
|
||||
raw_model = MinerModel.WHATSMINER.M50SVH30
|
||||
|
||||
expected_chips = 156
|
||||
|
||||
|
||||
class M50SVH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVH40
|
||||
raw_model = MinerModel.WHATSMINER.M50SVH40
|
||||
|
||||
|
||||
class M50SVH50(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SVH50
|
||||
raw_model = MinerModel.WHATSMINER.M50SVH50
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M50SPlusVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusVH30
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusVH30
|
||||
|
||||
|
||||
class M50SPlusVH40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusVH40
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusVH40
|
||||
|
||||
|
||||
class M50SPlusVJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusVJ30
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusVJ30
|
||||
|
||||
|
||||
class M50SPlusVK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusVK20
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusVK20
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
@@ -13,21 +13,21 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M50SPlusPlusVK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusPlusVK10
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusPlusVK10
|
||||
|
||||
expected_chips = 117
|
||||
|
||||
|
||||
class M50SPlusPlusVK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusPlusVK20
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusPlusVK20
|
||||
|
||||
|
||||
class M50SPlusPlusVK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M50SPlusPlusVK30
|
||||
raw_model = MinerModel.WHATSMINER.M50SPlusPlusVK30
|
||||
|
||||
expected_chips = 76
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M53VH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M53VH30
|
||||
raw_model = MinerModel.WHATSMINER.M53VH30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 128
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M53SVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M53SVH30
|
||||
raw_model = MinerModel.WHATSMINER.M53SVH30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M53SVJ40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M53SVJ40
|
||||
raw_model = MinerModel.WHATSMINER.M53SVJ40
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M53SPlusVJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M53SPlusVJ30
|
||||
raw_model = MinerModel.WHATSMINER.M53SPlusVJ30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M53SPlusPlusVK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M53SPlusPlusVK10
|
||||
raw_model = MinerModel.WHATSMINER.M53SPlusPlusVK10
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,12 +13,12 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M56VH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M56VH30
|
||||
raw_model = MinerModel.WHATSMINER.M56VH30
|
||||
|
||||
expected_hashboards = 4
|
||||
expected_chips = 108
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M56SVH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M56SVH30
|
||||
raw_model = MinerModel.WHATSMINER.M56SVH30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M56SPlusVJ30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M56SPlusVJ30
|
||||
raw_model = MinerModel.WHATSMINER.M56SPlusVJ30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,11 +13,11 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M59VH30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M59VH30
|
||||
raw_model = MinerModel.WHATSMINER.M59VH30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,21 +13,21 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M60VK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60VK10
|
||||
raw_model = MinerModel.WHATSMINER.M60VK10
|
||||
|
||||
|
||||
class M60VK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60VK20
|
||||
raw_model = MinerModel.WHATSMINER.M60VK20
|
||||
|
||||
|
||||
class M60VK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60VK30
|
||||
raw_model = MinerModel.WHATSMINER.M60VK30
|
||||
|
||||
|
||||
class M60VK40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60VK40
|
||||
raw_model = MinerModel.WHATSMINER.M60VK40
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M60SVK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60SVK10
|
||||
raw_model = MinerModel.WHATSMINER.M60SVK10
|
||||
|
||||
|
||||
class M60SVK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60SVK20
|
||||
raw_model = MinerModel.WHATSMINER.M60SVK20
|
||||
|
||||
|
||||
class M60SVK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60SVK30
|
||||
raw_model = MinerModel.WHATSMINER.M60SVK30
|
||||
|
||||
expected_chips = 78
|
||||
|
||||
|
||||
class M60SVK40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M60SVK40
|
||||
raw_model = MinerModel.WHATSMINER.M60SVK40
|
||||
|
||||
@@ -13,24 +13,24 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M63VK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63VK10
|
||||
raw_model = MinerModel.WHATSMINER.M63VK10
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M63VK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63VK20
|
||||
raw_model = MinerModel.WHATSMINER.M63VK20
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M63VK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63VK30
|
||||
raw_model = MinerModel.WHATSMINER.M63VK30
|
||||
|
||||
expected_chips = 68
|
||||
expected_hashboards = 4
|
||||
|
||||
@@ -13,23 +13,23 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M63SVK10(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63SVK10
|
||||
raw_model = MinerModel.WHATSMINER.M63SVK10
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M63SVK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63SVK20
|
||||
raw_model = MinerModel.WHATSMINER.M63SVK20
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M63SVK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M63SVK30
|
||||
raw_model = MinerModel.WHATSMINER.M63SVK30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,17 +13,17 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M66VK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M66VK20
|
||||
raw_model = MinerModel.WHATSMINER.M66VK20
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M66VK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M66VK30
|
||||
raw_model = MinerModel.WHATSMINER.M66VK30
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
@@ -13,18 +13,18 @@
|
||||
# See the License for the specific language governing permissions and -
|
||||
# limitations under the License. -
|
||||
# ------------------------------------------------------------------------------
|
||||
from pyasic.device.models import MinerModels
|
||||
from pyasic.device.models import MinerModel
|
||||
from pyasic.miners.device.makes import WhatsMinerMake
|
||||
|
||||
|
||||
class M66SVK20(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M66SVK20
|
||||
raw_model = MinerModel.WHATSMINER.M66SVK20
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
|
||||
class M66SVK30(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M66SVK30
|
||||
raw_model = MinerModel.WHATSMINER.M66SVK30
|
||||
|
||||
expected_chips = 96
|
||||
expected_hashboards = 4
|
||||
@@ -32,6 +32,6 @@ class M66SVK30(WhatsMinerMake):
|
||||
|
||||
|
||||
class M66SVK40(WhatsMinerMake):
|
||||
raw_model = MinerModels.WHATSMINER.M66SVK40
|
||||
raw_model = MinerModel.WHATSMINER.M66SVK40
|
||||
|
||||
expected_fans = 0
|
||||
|
||||
Reference in New Issue
Block a user