feature: improve iceriver support and add support for KS3M

This commit is contained in:
Upstream Data
2024-10-30 09:21:12 -06:00
parent 975560f46f
commit 7c18c9f69c
11 changed files with 40 additions and 4 deletions

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@@ -26,6 +26,7 @@ class MinerMake(str, Enum):
AURADINE = "Auradine"
EPIC = "ePIC"
BITAXE = "BitAxe"
ICERIVER = "IceRiver"
def __str__(self):
return self.value

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@@ -346,6 +346,7 @@ class BitAxeModels(str, Enum):
class IceRiverModels(str, Enum):
KS2 = "KS2"
KS3M = "KS3M"
def __str__(self):
return self.value

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@@ -15,7 +15,7 @@
# ------------------------------------------------------------------------------
from pyasic.miners.backends import AntminerModern
from pyasic.miners.device.models import KS3
from pyasic.miners.device.models.antminer import KS3
class BMMinerKS3(AntminerModern, KS3):

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@@ -165,13 +165,13 @@ class IceRiver(StockFirmware):
if web_userpanel is not None:
try:
for board in web_userpanel["boards"]:
idx = board["no"] - 1
idx = int(board["no"] - 1)
hb_list[idx].chip_temp = round(board["outtmp"])
hb_list[idx].temp = round(board["intmp"])
hb_list[idx].hashrate = AlgoHashRate.SHA256(
float(board["rtpow"].replace("G", "")), HashUnit.SHA256.GH
).into(self.algo.unit.default)
hb_list[idx].chips = board["chipnum"]
hb_list[idx].chips = int(board["chipnum"])
hb_list[idx].missing = False
except LookupError:
pass

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@@ -51,4 +51,4 @@ class BitAxeMake(BaseMiner):
class IceRiverMake(BaseMiner):
make = MinerMake.BITAXE
make = MinerMake.ICERIVER

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@@ -21,3 +21,4 @@ class KS2(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS2
expected_fans = 4
expected_chips = 18

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@@ -0,0 +1,24 @@
# ------------------------------------------------------------------------------
# Copyright 2024 Upstream Data Inc -
# -
# Licensed under the Apache License, Version 2.0 (the "License"); -
# you may not use this file except in compliance with the License. -
# You may obtain a copy of the License at -
# -
# http://www.apache.org/licenses/LICENSE-2.0 -
# -
# Unless required by applicable law or agreed to in writing, software -
# distributed under the License is distributed on an "AS IS" BASIS, -
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -
# See the License for the specific language governing permissions and -
# limitations under the License. -
# ------------------------------------------------------------------------------
from pyasic.device.models import MinerModel
from pyasic.miners.device.makes import IceRiverMake
class KS3M(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS3M
expected_fans = 4
expected_chips = 18

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@@ -1 +1,2 @@
from .KS2 import KS2
from .KS3 import KS3M

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@@ -463,6 +463,7 @@ MINER_CLASSES = {
MinerTypes.ICERIVER: {
None: type("IceRiverUnknown", (IceRiver, IceRiverMake), {}),
"KS2": IceRiverKS2,
"KS3M": IceRiverKS3M,
},
}

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@@ -0,0 +1,6 @@
from pyasic.miners.backends.iceriver import IceRiver
from pyasic.miners.device.models.iceriver import KS3M
class IceRiverKS3M(IceRiver, KS3M):
pass

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@@ -1 +1,2 @@
from .KS2 import IceRiverKS2
from .KS3 import IceRiverKS3M