add M32V20

This commit is contained in:
UpstreamData
2022-08-10 11:17:12 -06:00
parent b8239703c1
commit 5e9588cc56
5 changed files with 19 additions and 5 deletions

View File

@@ -22,3 +22,12 @@ class M32(BaseMiner):
self.model = "M32"
self.nominal_chips = 74
self.fan_count = 2
class M32V20(BaseMiner):
def __init__(self, ip: str):
super().__init__()
self.ip = ip
self.model = "M32 V20"
self.nominal_chips = 74
self.fan_count = 2

View File

@@ -19,5 +19,5 @@ from .M30S_Plus_Plus import M30SPlusPlus, M30SPlusPlusVG30, M30SPlusPlusVG40
from .M31S import M31S
from .M31S_Plus import M31SPlus, M31SPlusVE20
from .M32 import M32
from .M32 import M32, M32V20
from .M32S import M32S

View File

@@ -203,6 +203,7 @@ MINER_CLASSES = {
"M32": {
"Default": BTMinerM32,
"BTMiner": BTMinerM32,
"20": BTMinerM32V20,
},
"AvalonMiner 721": {
"Default": CGMinerAvalon721,

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@@ -13,12 +13,16 @@
# limitations under the License.
from pyasic.miners._backends import BTMiner # noqa - Ignore access to _module
from pyasic.miners._types import (
M32,
) # noqa - Ignore access to _module
from pyasic.miners._types import M32, M32V20 # noqa - Ignore access to _module
class BTMinerM32(BTMiner, M32):
def __init__(self, ip: str) -> None:
super().__init__(ip)
self.ip = ip
class BTMinerM32V20(BTMiner, M32V20):
def __init__(self, ip: str) -> None:
super().__init__(ip)
self.ip = ip

View File

@@ -34,5 +34,5 @@ from .M30S_Plus_Plus import (
from .M31S import BTMinerM31S
from .M31S_Plus import BTMinerM31SPlus, BTMinerM31SPlusVE20
from .M32 import BTMinerM32
from .M32 import BTMinerM32, BTMinerM32V20
from .M32S import BTMinerM32S