bug: use default chip count for bitaxe when asicCount is not set.

This commit is contained in:
upstreamdata
2024-07-01 23:08:31 -06:00
parent 7a9c9237a3
commit 427f91d677

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@@ -117,7 +117,7 @@ class BitAxe(BaseMiner):
).into(self.algo.unit.default),
chip_temp=web_system_info.get("temp"),
temp=web_system_info.get("vrTemp"),
chips=web_system_info.get("asicCount"),
chips=web_system_info.get("asicCount", 1),
expected_chips=self.expected_chips,
missing=False,
active=True,