Compare commits

...

9 Commits

Author SHA1 Message Date
Upstream Data
309356243b version: bump version number 2024-11-12 14:28:51 -07:00
Upstream Data
e9b4cc9bd6 feature: add Antminer D9 support 2024-11-12 14:28:31 -07:00
Upstream Data
648c54de93 bug: add iceriver KS5 chip count 2024-11-12 14:25:13 -07:00
Upstream Data
e1ce96ab1b bug: add innosilicon A11 chip count 2024-11-12 14:24:05 -07:00
Brett Rowan
86860a8dc4 version: bump version number 2024-11-08 09:18:34 -07:00
Jacob Roy
5212641f45 add json serialization to the Scheme class (#232) 2024-11-06 15:13:30 -07:00
Upstream Data
52432e6043 version: bump version number 2024-11-06 09:06:11 -07:00
Upstream Data
727e484860 docs: update docs 2024-11-06 09:05:08 -07:00
Upstream Data
6c091756d2 feature: add support for Iceriver KS5 and submodels 2024-11-06 09:04:38 -07:00
15 changed files with 140 additions and 3 deletions

View File

@@ -43,3 +43,24 @@
show_root_heading: false
heading_level: 4
## KS5 (Stock)
::: pyasic.miners.iceriver.iceminer.KSX.KS5.IceRiverKS5
handler: python
options:
show_root_heading: false
heading_level: 4
## KS5L (Stock)
::: pyasic.miners.iceriver.iceminer.KSX.KS5.IceRiverKS5L
handler: python
options:
show_root_heading: false
heading_level: 4
## KS5M (Stock)
::: pyasic.miners.iceriver.iceminer.KSX.KS5.IceRiverKS5M
handler: python
options:
show_root_heading: false
heading_level: 4

View File

@@ -688,6 +688,9 @@ details {
<li><a href="../iceriver/KSX#ks3-stock">KS3 (Stock)</a></li>
<li><a href="../iceriver/KSX#ks3l-stock">KS3L (Stock)</a></li>
<li><a href="../iceriver/KSX#ks3m-stock">KS3M (Stock)</a></li>
<li><a href="../iceriver/KSX#ks5-stock">KS5 (Stock)</a></li>
<li><a href="../iceriver/KSX#ks5l-stock">KS5L (Stock)</a></li>
<li><a href="../iceriver/KSX#ks5m-stock">KS5M (Stock)</a></li>
</ul>
</details>
</ul>

View File

@@ -23,7 +23,7 @@ from typing import Any, List, Union
from pyasic.config import MinerConfig
from pyasic.config.mining import MiningModePowerTune
from pyasic.data.pools import PoolMetrics
from pyasic.data.pools import PoolMetrics, Scheme
from .boards import HashBoard
from .device import DeviceInfo
@@ -154,7 +154,11 @@ class MinerData:
@staticmethod
def dict_factory(x):
return {k: v for (k, v) in x if not k.startswith("_")}
return {
k: v.value if isinstance(v, Scheme) else v
for (k, v) in x
if not k.startswith("_")
}
def __post_init__(self):
self._datetime = datetime.now(timezone.utc).astimezone()

View File

@@ -16,6 +16,7 @@ class AntminerModels(str, Enum):
S9i = "S9i"
S9j = "S9j"
T9 = "T9"
D9 = "D9"
Z15 = "Z15"
Z15Pro = "Z15 Pro"
S17 = "S17"
@@ -355,6 +356,9 @@ class IceRiverModels(str, Enum):
KS3 = "KS3"
KS3L = "KS3L"
KS3M = "KS3M"
KS5 = "KS5"
KS5L = "KS5L"
KS5M = "KS5M"
def __str__(self):
return self.value

View File

@@ -0,0 +1,22 @@
# ------------------------------------------------------------------------------
# Copyright 2022 Upstream Data Inc -
# -
# Licensed under the Apache License, Version 2.0 (the "License"); -
# you may not use this file except in compliance with the License. -
# You may obtain a copy of the License at -
# -
# http://www.apache.org/licenses/LICENSE-2.0 -
# -
# Unless required by applicable law or agreed to in writing, software -
# distributed under the License is distributed on an "AS IS" BASIS, -
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -
# See the License for the specific language governing permissions and -
# limitations under the License. -
# ------------------------------------------------------------------------------
from pyasic.miners.backends import AntminerModern
from pyasic.miners.device.models import D9
class BMMinerD9(AntminerModern, D9):
pass

View File

@@ -14,6 +14,7 @@
# limitations under the License. -
# ------------------------------------------------------------------------------
from .D9 import BMMinerD9
from .E9 import BMMinerE9Pro
from .S9 import BMMinerS9, BMMinerS9i, BMMinerS9j
from .T9 import BMMinerT9

View File

@@ -0,0 +1,23 @@
# ------------------------------------------------------------------------------
# Copyright 2022 Upstream Data Inc -
# -
# Licensed under the Apache License, Version 2.0 (the "License"); -
# you may not use this file except in compliance with the License. -
# You may obtain a copy of the License at -
# -
# http://www.apache.org/licenses/LICENSE-2.0 -
# -
# Unless required by applicable law or agreed to in writing, software -
# distributed under the License is distributed on an "AS IS" BASIS, -
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -
# See the License for the specific language governing permissions and -
# limitations under the License. -
# ------------------------------------------------------------------------------
from pyasic.device.models import MinerModel
from pyasic.miners.device.makes import AntMinerMake
class D9(AntMinerMake):
raw_model = MinerModel.ANTMINER.D9
expected_chips = 126

View File

@@ -14,6 +14,7 @@
# limitations under the License. -
# ------------------------------------------------------------------------------
from .D9 import D9
from .E9 import E9Pro
from .S9 import S9, S9i, S9j
from .T9 import T9

View File

@@ -0,0 +1,37 @@
# ------------------------------------------------------------------------------
# Copyright 2024 Upstream Data Inc -
# -
# Licensed under the Apache License, Version 2.0 (the "License"); -
# you may not use this file except in compliance with the License. -
# You may obtain a copy of the License at -
# -
# http://www.apache.org/licenses/LICENSE-2.0 -
# -
# Unless required by applicable law or agreed to in writing, software -
# distributed under the License is distributed on an "AS IS" BASIS, -
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -
# See the License for the specific language governing permissions and -
# limitations under the License. -
# ------------------------------------------------------------------------------
from pyasic.device.models import MinerModel
from pyasic.miners.device.makes import IceRiverMake
class KS5(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS5
expected_fans = 4
expected_chips = 92
class KS5L(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS5L
expected_fans = 4
expected_chips = 18
class KS5M(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS5M
expected_fans = 4

View File

@@ -2,3 +2,4 @@ from .KS0 import KS0
from .KS1 import KS1
from .KS2 import KS2
from .KS3 import KS3, KS3L, KS3M
from .KS5 import KS5, KS5L, KS5M

View File

@@ -21,3 +21,4 @@ class A11(InnosiliconMake):
raw_model = MinerModel.INNOSILICON.A11
expected_hashboards = 4
expected_chips = 8

View File

@@ -74,6 +74,7 @@ MINER_CLASSES = {
"ANTMINER L7": BMMinerL7,
"ANTMINER K7": BMMinerK7,
"ANTMINER E9 PRO": BMMinerE9Pro,
"ANTMINER D9": BMMinerD9,
"ANTMINER S9": BMMinerS9,
"ANTMINER S9I": BMMinerS9i,
"ANTMINER S9J": BMMinerS9j,
@@ -473,6 +474,9 @@ MINER_CLASSES = {
"KS3": IceRiverKS3,
"KS3L": IceRiverKS3L,
"KS3M": IceRiverKS3M,
"KS5": IceRiverKS5,
"KS5L": IceRiverKS5L,
"KS5M": IceRiverKS5M,
},
}

View File

@@ -0,0 +1,14 @@
from pyasic.miners.backends.iceriver import IceRiver
from pyasic.miners.device.models.iceriver import KS5, KS5L, KS5M
class IceRiverKS5(IceRiver, KS5):
pass
class IceRiverKS5L(IceRiver, KS5L):
pass
class IceRiverKS5M(IceRiver, KS5M):
pass

View File

@@ -2,3 +2,4 @@ from .KS0 import IceRiverKS0
from .KS1 import IceRiverKS1
from .KS2 import IceRiverKS2
from .KS3 import IceRiverKS3, IceRiverKS3L, IceRiverKS3M
from .KS5 import IceRiverKS5, IceRiverKS5L, IceRiverKS5M

View File

@@ -1,6 +1,6 @@
[tool.poetry]
name = "pyasic"
version = "0.62.1"
version = "0.62.4"
description = "A simplified and standardized interface for Bitcoin ASICs."
authors = ["UpstreamData <brett@upstreamdata.ca>"]
repository = "https://github.com/UpstreamData/pyasic"