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bug: add iceriver KS5 chip count

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2024-11-12 14:25:13 -07:00
parent e1ce96ab1b
commit 648c54de93
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pyasic/miners/device/models/iceriver/KSX/KS5.py
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@@ -21,6 +21,7 @@ class KS5(IceRiverMake):
raw_model = MinerModel.ICERIVER.KS5 raw_model = MinerModel.ICERIVER.KS5
expected_fans = 4 expected_fans = 4
expected_chips = 92
class KS5L(IceRiverMake): class KS5L(IceRiverMake):