From 4dc5b1a5410a5f2df173126c6249b1c676898242 Mon Sep 17 00:00:00 2001
From: Upstream Data <brett@upstreamdata.ca>
Date: Wed, 30 Oct 2024 08:44:08 -0600
Subject: [PATCH] feature: add chip count for WM M60VK20

---
 pyasic/miners/device/models/whatsminer/M6X/M60.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/pyasic/miners/device/models/whatsminer/M6X/M60.py b/pyasic/miners/device/models/whatsminer/M6X/M60.py
index 2f3418a2..abbbfe4b 100644
--- a/pyasic/miners/device/models/whatsminer/M6X/M60.py
+++ b/pyasic/miners/device/models/whatsminer/M6X/M60.py
@@ -24,6 +24,8 @@ class M60VK10(WhatsMinerMake):
 class M60VK20(WhatsMinerMake):
     raw_model = MinerModel.WHATSMINER.M60VK20
 
+    expected_chips = 172
+
 
 class M60VK30(WhatsMinerMake):
     raw_model = MinerModel.WHATSMINER.M60VK30