CAT_TOM/pyasic
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feature: add M30S++ VH70 chip count.

Browse Source
This commit is contained in:
UpstreamData
2023-02-22 11:43:22 -07:00
parent b0f7629607
commit 34389e9133
1 changed files with 1 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
pyasic/miners/_types/whatsminer/M3X/M30S_Plus_Plus.py
View File

@@ -192,10 +192,7 @@ class M30SPlusPlusVH70(WhatsMiner): # noqa - ignore ABC method implementation
super().__init__() super().__init__()
self.ip = ip self.ip = ip
self.model = "M30S++ VH70" self.model = "M30S++ VH70"
self.nominal_chips = 0 self.nominal_chips = 70
warnings.warn(
"Unknown chip count for miner type M30S++ VH70, please open an issue on GitHub (https://github.com/UpstreamData/pyasic)."
)
self.fan_count = 2 self.fan_count = 2